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--exp_sig_gen
--Created (25.08.2011)
--Created by Alina Ivanova
--Modified (date, by whom)
--Version 1.0
--test exponentional signal generator
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-------------------------------------------------------------------------------
-- VHDL exp_sig_gen
-------------------------------------------------------------------------------
library ieee;
use     ieee.std_logic_1164.all;
use     ieee.std_logic_unsigned.all;

library altera_mf;
use altera_mf.all;

entity exp_sig_gen is
	port(
		reset                                                   : in  std_logic;
		clk                                                     : in  std_logic;
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		output_data                                             : out std_logic_vector (5 downto 0));
end exp_sig_gen;
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architecture functional of exp_sig_gen is
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	signal rom_data_out                                        : std_logic_vector (5 downto 0);
	signal rm_addr                                             : std_logic_vector (6 downto 0);
	signal signal_data                                         : std_logic;
	signal signal_bus                                          : std_logic_vector (5 downto 0);
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	component rom_exp_sig_gen
		port(
			address                                              : in  std_logic_vector (6 downto 0);
			clock                                                : in  std_logic:= '1';
			q                                                    : out std_logic_vector (5 downto 0));
	end component;
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begin
	RomExpSigGen: rom_exp_sig_gen port map(
		address                                                 => rm_addr(6 downto 0),
		clock                                                   => clk,
		q                                                       => rom_data_out);

	Process_1: process (clk, reset)
	begin
		if (reset = '0') then
			signal_bus                                         <= (others => '0');
			signal_data                                        <= '0';
		elsif (rising_edge(clk)) then
			signal_bus                                         <= "111000";
			signal_data                                        <= '1';
		end if;
	end process Process_1;
end functional;
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